NDLI: Large-area ∼20% efficient silicon solar cells using fine line direct printing

Content Provider	IEEE Xplore Digital Library
Author	Jiun-Hong Lai Cooper, I.B. Xudong Chen Church, K. Haixin Yang Rohatg, A.
Copyright Year	2012
Description	Author affiliation: Regent's Professor, Georgia Institute of Technology, USA (Rohatg, A.) \|\| nScrypt Inc, 12151 Research Pkwy, suite 150, Orlando, Florida, 32826, USA (Xudong Chen; Church, K.) \|\| University Center of Excellence for Photovoltaics, Georgia Institute of Technology, Atlanta, 30332 USA (Jiun-Hong Lai; Cooper, I.B.) \|\| DuPont Microcircuit Materials, 14 T. W. Alexander Drive, Research Triangle Park, NC 27709, USA (Haixin Yang)
Abstract	This paper presents the use of a finer line printing technology for achieving over 20.2% efficient cells with oxide/nitride rear passivation and screen-printed local back contacts on large-area (239 $cm^{2})$ commercial grade Cz Si wafers. The front metal gridlines are printed by a one-step non-contact approach of a modified silver printable paste. The line width is as narrow as 55µm, and the line height is more than 35µm after firing in a conventional belt furnace. The significantly reduced metal converge on the front side resulted in reduced shadowing loss and an increase in absolute cell efficiency of ∼0.5% compared to the screen-printed reference solar cells. Increasing the number of gridlines from 74 to 83 in conjunction with reduced line width from 100 µm to 55 µm increased the J by ∼0.5 $mA/cm^{2}$ to 38.4 $mA/cm^{2}.$ This combined with a V of 657 mV and FF of 80.0% produced the 20.2% efficient cell compared to a 19.7% screen-printed cell.
Starting Page	002192
Ending Page	002195
File Size	341120
Page Count	4
File Format	PDF
ISBN	9781467300643
ISSN	01608371
e-ISBN	9781467300667
DOI	10.1109/PVSC.2012.6318031
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Artificial intelligence Printing Abstracts Silicon compounds Heating Annealing Microscopy
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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