NDLI: Diagnostic structures for epitaxial thin silicon solar cells

Content Provider	IEEE Xplore Digital Library
Author	Murcia, C.P. Ruiying Hao Creazzo, T. Shreve, K. Lochtefeld, A. Curtin, M. Barnett, A.
Copyright Year	2010
Description	Author affiliation: Solar Power Program University of Delaware, Newark, United States (Murcia, C.P.; Ruiying Hao; Creazzo, T.; Shreve, K.; Barnett, A.) \|\| AmberWave Systems, Salem, NH, United States (Lochtefeld, A.; Curtin, M.)
Abstract	The value of a high performance thin silicon solar cell is based on high open circuit voltage (Voc) which is highly dependent upon surface and interface recombination. A microelectronic approach with the series and parallel fabrication of different device structures is presented. This approach includes the fabrication of planar solar cells based on different solar cell designs that maximize Voc. Subsequently, using the same solar cell design, more advanced epitaxial growth test structures were fabricated on the same substrate to understand recombination losses and Voc. In high performance thin silicon solar cells, Voc is highly sensitive to surface recombination. Achieving a good surface and interface passivation in epitaxial silicon solar cells is a challenge, especially for the absorber back surface. In this work, we used test structures embedded in the solar cells to independently optimize Voc and the back surface of a thin epitaxial absorber as well as other silicon interfaces. Most epitaxial thin silicon solar cells are fabricated with in-situ processes that lead to difficulties in the independent optimization of such surfaces. To contribute to the design space in thin silicon solar cells, we tested basic device designs and test structures that lead to high Voc. The design of basic structures is important to measure parameters that limit voltage. This is a diagnostic tool for the fabrication of high performance thin silicon solar cells. This work reports device results that exhibit a path to high open circuit voltage, determined by device design, interface recombination, and bulk lifetime. With independent optimization of parameters that limit Voc and therefore performance, this work contributes to the understanding of thin silicon solar cells.
Starting Page	002204
Ending Page	002207
File Size	3266482
Page Count	4
File Format	PDF
ISBN	9781424458905
ISSN	01608371
e-ISBN	9781424458929
DOI	10.1109/PVSC.2010.5616090
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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