NDLI: A novel output baseline holder circuit for CMOS front-end analog channels

Content Provider	IEEE Xplore Digital Library
Author	Corsi, F. Foresta, M. Marzocca, C. Matarrese, G. Tauro, A.
Copyright Year	2008
Description	Author affiliation: Politecnico di Bari, Dipartimento di Elettrotecnica ed Elettronica, I70125 Italy (Corsi, F.; Foresta, M.; Marzocca, C.; Matarrese, G.) \|\| CERN, Geneva, Switzerland (Tauro, A.)
Abstract	We propose a novel CMOS baseline holder circuit, able to keep at a specified value the dc output voltage of typical integrated front-end analog channels coupled to silicon detectors, for both high energy physics and medical imaging applications. The circuit, together with the shaping filter, forms a slow feedback loop. A very low frequency pole is obtained in the feedback path, without using large capacitance values, by exploiting a circuit technique based on the properties of operational transconductance amplifiers. The huge time constant achievable with the proposed technique makes this solution suitable to be applied to high-gain front-end circuits, since the stability conditions can be easily fulfilled. Two different non-linearity effects are exploited to limit the baseline shift which occurs at high signal rates. The circuit has been designed in a standard CMOS 0.35μm technology and the first experimental results obtained from different prototypes show the effectiveness of the proposed solution.
Starting Page	1476
Ending Page	1481
File Size	7421062
Page Count	6
File Format	PDF
ISBN	9781424427147
ISSN	10957863
DOI	10.1109/NSSMIC.2008.4774694
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-19
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS analog integrated circuits Feedback circuits CMOS technology Voltage Coupling circuits Silicon Detectors Biomedical imaging Filters Feedback loop
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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