NDLI: PADI, a fast Preamplifier - Discriminator for Time-of-Flight measurements

Content Provider	IEEE Xplore Digital Library
Author	Ciobanu, M. Herrmann, N. Hildenbrand, K. D. Kis, M. Schuttauf, A.
Copyright Year	2008
Description	Author affiliation: GSI Helmholtzzentrum, Darmstadt, Germany (Hildenbrand, K. D.; Kis, M.; Schuttauf, A.) \|\| Physikalisches Institut der Universität Heidelberg, Germany (Ciobanu, M.; Herrmann, N.)
Abstract	We designed a general purpose PreAmplifier-DIscriminator (PADI) ASIC to be used as Front-End-Electronics (FEE) for readout of timing Resistive Plates Chamber (RPC) detectors in the CBM experiment at FAIR. Our design is derived from the NINO architecture that was the first ASIC realization of a low power FEE. The PADI-chip can be used for different types of RPC’s, with strip- or pad- anode structures (HADES, FOPI, and ALICE) or for diamond detectors. These fast timing detectors reveal signal rise times t≪500 ps and generate a prompt charge usually in the range of 50 to 2000 fC. An intrinsic time resolution of σ≪50 ps is demonstrated with RPC’s, which requires a preamplifier-discriminator stage of an intrinsic electronic resolution of σ ≪15 ps. The first prototype developed is a three-channel PADI-ASIC in 0.18 μm CMOS technology. It has the following design: fully differential, with 50 Ω input impedance at a preamplifier gain of G≫ 100 and a bandwidth of BW≫ 200 MHz; it shows a signal peaking time of t≪ 1ns and a noise of V ≪ 32 μV referred to the input. The preamplifier use a DC feedback loop for the offset and threshold stabilization with a threshold range between ±100 mV. The discriminator has a gain of G≫100. These key parameters of the PADI-1 chip assure an excellent intrinsic electronic resolution of σ≪ 15 ps and a low power consumption of P≪ 30 mW/ch. As an auxiliary function, PADI-1 offers an analogue signal for the slewing correction. In this article, we present the first measurements from PADI-1 discussing its gain, linearity, bandwidth, noise, and time-over-threshold (ToT)- behavior, as well as timing performance, crosstalk, common-mode-rejection and input impedance. In order to investigate its rate capability and stability in experimental conditions, we tested PADI-1 in two experiments using diamond detectors. We present also the successive designs: PADI-2, 3, which are four channels versions, optimized to maximize the preamplifier bandwidth still maintaining the 50 Ω input impedance. Both have OR-in/out pins to daisy-chain them e.g. for trigger purposes. PADI-4 is a 4 channel version with increased input impedance for the read out of diamond detectors.
Starting Page	2018
Ending Page	2024
File Size	5809286
Page Count	7
File Format	PDF
ISBN	9781424427147
ISSN	10957863
DOI	10.1109/NSSMIC.2008.4774801
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-19
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Preamplifiers Detectors Impedance Timing Bandwidth Crosstalk Application specific integrated circuits Signal resolution Tellurium CMOS technology
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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