NDLI: Readout and timing system prototypes for DETNI

Content Provider	IEEE Xplore Digital Library
Author	Kemmerling, G. Borga, A. Erven, W. Gebauer, B. Schulz, Ch. Thielmann, C.
Copyright Year	2008
Description	Author affiliation: Forschungszentrum, Jülich GmbH, Zentralinstitut für Elektronik, D-52425 Germany (Kemmerling, G.; Borga, A.; Erven, W.; Thielmann, C.) \|\| Helmholtz-Zentrum Berlin für Materialien und Energie GmbH, Bereich Strukturforschung SF1, D-14109 Germany (Gebauer, B.; Schulz, Ch.)
Abstract	Within the DETNI project prototypes of three novel position sensitive thermal neutron detectors types and adequate readout electronics have been developed. The detectors are based on thin solid neutron converters together with two-dimensional readout structures for the detection of secondary particles induced by the neutron capture. They aim at global count rates of up to 100 MHz together with a high spatial and time resolution. In order to utilize these detector characteristics new frontend and data acquisition electronics was required. A novel channel-wise self-triggered ASIC has been developed, which is able to cope with such high count rates and which complies with the signal specifications of the three different detector types. It provides time and analog information of a neutron event with a time resolution of 2 ns. For the data acquisition electronics, which will be described in this paper, prototypes of a clock distribution system and of a FPGA based readout system have been developed with current state-of-the-art electronics. The clock distribution system is to provide high precision, high frequency clock signals to the frontend, which is required to achieve the desired time resolution. The FPGA based readout system is to read out time stamp and analog information of the ASICs, carry out the digitization and transmit the data stream to a host PC
Starting Page	2180
Ending Page	2184
File Size	7895568
Page Count	5
File Format	PDF
ISBN	9781424427147
ISSN	10957863
DOI	10.1109/NSSMIC.2008.4774784
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-19
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Prototypes Neutrons Signal resolution Clocks Data acquisition Field programmable gate arrays Position sensitive particle detectors Readout electronics Spatial resolution
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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