NDLI: Digital architecture and interface of the new ATLAS Pixel Front-End IC for upgraded LHC luminosity

Content Provider	IEEE Xplore Digital Library
Author	Arutinov, David Barbero, Marlon Beccherle, Roberto Buscher, Volker Darbo, Giovanni Ely, Robert Fougeron, Denis Garcia-Sciveres, Maurice Gnani, Dario Hemperek, Tomasz Karagounis, Michael Kluit, Ruud Kostyukhin, Vadim Mekkaoui, Abderrezak Menouni, Moshine Schipper, Jan David Wermes, Norbert
Copyright Year	2008
Description	Author affiliation: CPPM Aix-Marseille Université, CNRS/IN2P3, France (Fougeron, Denis; Menouni, Moshine) \|\| Institute of Physics, Bonn, 53115 Germany (Arutinov, David; Barbero, Marlon; Buscher, Volker; Hemperek, Tomasz; Karagounis, Michael; Wermes, Norbert) \|\| NIKHEF, 1098 SJ Amsterdam, The Netherlands (Kluit, Ruud; Schipper, Jan David) \|\| INFN Genova, 33 - 16146 Italy (Beccherle, Roberto; Darbo, Giovanni; Kostyukhin, Vadim) \|\| Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720, USA (Ely, Robert; Garcia-Sciveres, Maurice; Gnani, Dario; Mekkaoui, Abderrezak)
Abstract	A new pixel Front-End Integrated Circuit is being developed in a 130nm technology for use in the foreseen b-layer upgrade of the ATLAS Pixel Detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the End-of-Column, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.
Starting Page	1923
Ending Page	1928
File Size	5671827
Page Count	6
File Format	PDF
ISBN	9781424427147
ISSN	10957863
DOI	10.1109/NSSMIC.2008.4774765
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-19
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital integrated circuits Large Hadron Collider Detectors Iron Logic Physics Buffer storage Prototypes Nuclear and plasma sciences Integrated circuit technology
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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