NDLI: A versatile digital readout system for the PANDA MVD

Content Provider	IEEE Xplore Digital Library
Author	Mertens, Marius C. Hugging, Fabian Ritman, James Stockmanns, Tobias
Copyright Year	2008
Description	Author affiliation: Forschungszentrum Jülich GmbH, Germany (Mertens, Marius C.; Ritman, James; Stockmanns, Tobias) \|\| Physikalisches Institut, Universität, Bonn, Germany (Hugging, Fabian)
Abstract	The Micro Vertex Detector (MVD) for the PANDA experiment at the future Facility for Antiproton and Ion Research (FAIR) will be the innermost high precision vertexing detector, necessary for e.g. identification of displaced vertices of D-meson decays. Challenges include its triggerless readout and a high occupancy due to its proximity to the interaction point. Thus, the MVD design foresees hybrid silicon pixel sensors for the inner layers, silicon strip sensors for the outer layers and a custom frontend chip which can sustain high data rates for the readout. During the development of the MVD, a flexible system is needed to test pixel and strip detector prototypes. Both the suitability of existing concepts and newly developed circuits have to be evaluated. In the following, a versatile digital readout system for device testing and evaluation on a tabletop scale is presented along with application examples from practical use. Its FPGA-based hardware, modular firmware and software are the key features which provide great flexibility and ease of use at the same time.
Starting Page	3430
Ending Page	3433
File Size	2491515
Page Count	4
File Format	PDF
ISBN	9781424427147
ISSN	10957863
DOI	10.1109/NSSMIC.2008.4775077
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-19
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Silicon Strips Circuit testing System testing Software prototyping Prototypes Application software Hardware Microprogramming Reconfigurable architectures Field programmable gate arrays Data acquisition Digital circuits
Content Type	Text
Resource Type	Article

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