NDLI: A modular DAQ system for ultra-fast sampling for application in High Energy and Astroparticle physics

Content Provider	IEEE Xplore Digital Library
Author	Bitossi, M. Paoletti, R. Pegna, R.
Copyright Year	2008
Description	Author affiliation: University of Siena & INFN Gruppo Collegato Siena, Via Roma 56, 53100, ITALY (Paoletti, R.; Pegna, R.) \|\| INFN Sez. Pisa & University of Pisa, Largo B. Pontecorvo 3, 56127, ITALY (Bitossi, M.)
Abstract	We present a new compact Acquisition System suitable for use with detectors for High Energy and Astroparticle. An interface board, called CAPR1 (CAlibration PRotocol ONE), receives the analog signals and provides the proper impedance matching with the possibility to select the desired polarity and change the input common mode. The signals are transmitted differentially to a second board, called DRS2 mezzanine where sampling and digitizing are performed. The DRS2 mezzanine is based on a low power analog sampler (Domino Ring Sampler) with frequency ranging from 1 to 4.5 GHz, while the data are digitized by two 12-bit resolution ADCs at 40 MHz for a total of 20 channels. Up to four DRS2 mezzanines are placed on a 9U VME motherboard called PULSAR (PULSer And Recorder), that performs data handling and reformatting. Since the current version of Domino Ring Sampler (DRS2) chip shows a non-linear behaviour, a data calibration procedure is necessary. This task is executed on the interface board by setting DC levels on a calibration path in place of the input signals. The calibration points for every DC value are extrapolated from the sampled data and the calibration curve is obtained. The DC levels are set by the motherboard using an SPI protocol through the same cable that is used for the analog transmission. Every PULSAR hosts up to 80 analog channels plus auxiliary digital signals for trigger and monitor purposes. The data are transferred to PCI memory via Gbit optical links using the CERN S-Link. The Data Acquisition system design and performances are described in detail.
Starting Page	2143
Ending Page	2145
File Size	2273829
Page Count	3
File Format	PDF
ISBN	9781424427147
ISSN	10957863
DOI	10.1109/NSSMIC.2008.4774921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-19
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data acquisition Sampling methods Physics Calibration Protocols Detectors Impedance matching Frequency Signal resolution Data handling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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