NDLI: Fault and simple power attack resistant RSA using Montgomery modular multiplication

Content Provider	IEEE Xplore Digital Library
Author	Fournaris, A.P.
Copyright Year	2010
Description	Author affiliation: Hitachi Europe SAS, Information and Communication Technologies Lab. (ICTL), European R-D Center (ERD), Sophia Antipolis, France (Fournaris, A.P.)
Abstract	Side channel attacks and more specifically fault, simple power attacks, constitute a pragmatic, potent mean of braking a cryptographic algorithm like RSA. For this reason, many researchers have proposed modifications on the arithmetic operation functions required for RSA in order to thwart those attacks. However, these modifications are applied on theoretic — algorithmic level and do not necessary result in high performance RSA designs. This paper constitute the first complete attempt for an efficient design approach on a fault and simple power attack resistant RSA based on the well known, for its high performance, Montgomery multiplication algorithm. To achieve this, a fault and simple power attack resistant modular exponentiation algorithm is proposed that is based on the Montgomery modular multiplication. In order to optimize this algorithm's performance we also propose a modified version of Montgomery modular multiplication algorithm that employs value precomputation and carry save logic in all input, output and intermediate values. We introduce a hardware architecture based on the proposed Montgomery modular multiplication algorithm and use it as a building block for the design of a fault and simple power attack resistant modular exponentiation unit. This unit is optimized by taking advantage of the inherit parallelism in the proposed fault and simple power attack resistant modular exponentiation algorithm. Realizing the proposed unit in FPGA technology very advantageous results are found when compared against other well known designs even though our design bears an extra computation cost due to its fault and simple power attack resistance characteristic.
Starting Page	1875
Ending Page	1878
File Size	1979314
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537879
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Cryptography Arithmetic Logic Hardware Parallel processing Field programmable gate arrays Computational efficiency
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Efficient Montgomery Multiplication Algorithm and RSA Cryptographic Processor

FPGA implementation of modified serial montgomery modular multiplication for 2048-bit RSA cryptosystems

Montgomery Exponentiation with No Final Comparisons: Improved Results

Power Analysis of a Montgomery Modular Multiplier for Cryptosystems

Montgomery modular exponentiation on FPGA

High radix montgomery modular multiplication on FPGA

A novel fast modular multiplier architecture for 8,192-bit RSA cryposystem

Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation

An Implementation of Montgomery Modular Multiplication on FPGAs

Fault and simple power attack resistant RSA using Montgomery modular multiplication

Similar Documents

An Efficient Montgomery Multiplication Algorithm and RSA Cryptographic Processor

FPGA implementation of modified serial montgomery modular multiplication for 2048-bit RSA cryptosystems

Montgomery Exponentiation with No Final Comparisons: Improved Results

Power Analysis of a Montgomery Modular Multiplier for Cryptosystems

Montgomery modular exponentiation on FPGA

High radix montgomery modular multiplication on FPGA

A novel fast modular multiplier architecture for 8,192-bit RSA cryposystem

Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation

An Implementation of Montgomery Modular Multiplication on FPGAs

Fault and simple power attack resistant RSA using Montgomery modular multiplication