NDLI: Foreground digital calibration of non-linear errors in pipelined A/D converters

Content Provider	IEEE Xplore Digital Library
Author	Adel, H. Dessouky, M. Louerat, M. Gicquel, H. Haddara, H.
Copyright Year	2010
Description	Author affiliation: STMicroelectronics, Grenoble, France (Gicquel, H.) \|\| LIP6 Laboratory, Pierre & Marie Curie University, France (Adel, H.; Dessouky, M.; Louerat, M.) \|\| Ain Shams University, Egypt (Haddara, H.)
Abstract	A foreground digital calibration technique for pipelined ADC is proposed which accounts for linear error correction, while an error estimation technique for amplifier non-linearity is suggested as a reference for non-linear error correction. The calibration algorithm is based on applying a slow input to the ADC to automatically correct for linear errors, while depending on the accuracy of Digital Error Correction (DEC) to estimate and correct for non-linear errors. The proposed calibration scheme is demonstrated for an 11 bit pipelined ADC, and gives SNDR improvement over 30 dB, while using low specifications residue amplifier to reduce power consumption.
Starting Page	569
Ending Page	572
File Size	498679
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537533
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Error correction Error analysis Energy consumption Digital circuits Laboratories Redundancy Nonlinear distortion Analog circuits Temperature
Content Type	Text
Resource Type	Article

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