NDLI: Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed

Content Provider	IEEE Xplore Digital Library
Author	Alioto, M. Bennati, P. Giorgi, R.
Copyright Year	2010
Description	Author affiliation: Department of Information Engineering, University of Siena, Siena, Italy (Alioto, M.; Bennati, P.; Giorgi, R.)
Abstract	In this paper, a technique to reduce the leakage power consumption in embedded drowsy instruction caches (I caches) is proposed. The technique is called “Improved Drowsy” (ID), and adopts a more efficient strategy than standard Drowsy Caches (DCs) to turn off unused cache lines, based on locality. The implementation of ID caches requires minor changes, and the area/speed overhead associated with the additional circuitry is insignificant. The proposed technique is assessed through circuit and cycle accurate simulations on an L1 instruction cache embedded in an ARM XScale processor based system in a 65 nm CMOS technology. Results show that this technique is able to reduce the leakage power by 69% on average. Leakage of DC is shown to be significantly lowered with the proposed ID approach, being DC leakage greater than that of ID by up to 53%, and 10 15% typically.
Starting Page	37
Ending Page	40
File Size	177153
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537105
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Circuit simulation CMOS technology Space technology Cache memory Voltage control Power engineering and energy Distributed control CMOS process Signal design
Content Type	Text
Resource Type	Article

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