NDLI: A 22.4 mW competitive fuzzy edge detection processor for volume rendering

Content Provider	IEEE Xplore Digital Library
Author	Joonsoo Kwon Minsu Kim Jinwook Oh Hoi-Jun Yoo
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea (Joonsoo Kwon; Minsu Kim; Jinwook Oh; Hoi-Jun Yoo)
Abstract	A low power competitive fuzzy edge detection (C-FED) processor is proposed for gradient calculations in volume rendering. Its linearized fuzzy membership function reduces overall power by 35.1% and the proposed hardware sharing between computation stages reduces power consumption by 18%. Threshold adaptive bit control scheme is proposed to predetermine background pixel with simple operation which results in 13% power reduction. Overall power consumption is reduced by 53.8%. Its power consumption and energy per pixel is 22.4 mW and 0.14nJ/pixel, respectively, at 1.8-V supply. The fabricated processor occupying 450 μm × 450 μm in a 0.18 μm CMOS process achieves 1821.5fps for the input image of 300 × 300 pixels at 200 MHz operating frequency.
Starting Page	1883
Ending Page	1886
File Size	1304661
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537899
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image edge detection Energy consumption Hardware Programmable control Adaptive control Noise robustness CMOS process Pixel Rendering (computer graphics) Power engineering computing
Content Type	Text
Resource Type	Article

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