NDLI: Fast hard multiple generators for radix-8 Booth encoded modulo $2^{n}−1$ and modulo $2^{n}+1$ multipliers

Content Provider	IEEE Xplore Digital Library
Author	Muralidharan, R. Chip-Hong Chang
Copyright Year	2010
Description	Author affiliation: Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore (Muralidharan, R.; Chip-Hong Chang)
Abstract	Hard multiple generation is the bottleneck operation in radix-8 Booth encoded modulo $2^{n}−1$ and modulo $2^{n}+1$ multipliers. In this paper, fast hard multiple generators for the moduli $2^{n}−1$ and $2^{n}+1$ are proposed. They are implemented as parallel-prefix structures based on the simplified carry equations. Synthesis results based on TSMC 0.18μm, 1.8V CMOS standard-cell library show that the proposed modulo $2^{n}−1$ hard multiple generator reduces the critical path delay of the fastest general-purpose modulo $2^{n}−1$ adder by 12% and 10% for n = 8 and n = 64, respectively. Compared to the smallest modulo $2^{n}−1$ adder, the proposed design leads to 19% and 12% savings in silicon area for n = 8 and n = 64, respectively. The proposed modulo $2^{n}+1$ hard multiple generator also has the least critical path delay among the existing modulo $2^{n}+1$ adders.
Starting Page	717
Ending Page	720
File Size	263242
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537480
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Delay Equations Arithmetic Concurrent computing Embedded system Libraries Silicon Digital filters Convolvers
Content Type	Text
Resource Type	Article

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