NDLI: An improved soft BCH decoder with one extra error compensation

Content Provider	IEEE Xplore Digital Library
Author	Yi-Min Lin Hsie-Chia Chang Chen-Yi Lee
Copyright Year	2010
Description	Author affiliation: Department of Electronics Engineering & Institute of Electronics National Chiao Tung University, Hsinchu, Taiwan, R.O.C. (Yi-Min Lin; Hsie-Chia Chang; Chen-Yi Lee)
Abstract	In existing soft decision algorithms, a soft BCH decoders provides better error correcting performance but has much higher hardware complexity than a traditional hard BCH decoder. In this paper, a soft BCH decoder with both better error correcting performance and lower complexity is presented. The low complexity feature of the proposed architecture is achieved by dealing with least reliable bits. By compensating extra one error outside the least reliable set, the error correcting ability is improved. In addition, the proposed error locator evaluator evaluates error locations without Chien search, leading to high throughput. As compared with the traditional hard BCH decoder, the experimental result reveals that our proposed improved soft BCH decoder can achieve 0.75db coding gain for BCH (255,239) code. Implemented in standard CMOS 90nm technology, it can reach 316.3Mb/s throughput at 360MHz operation frequency with gate-count of 4.06K according to the post-layout simulations.
Starting Page	3941
Ending Page	3944
File Size	267916
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537672
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Error compensation Error correction Hardware Throughput CMOS technology Bit error rate Polynomials Frequency Digital video broadcasting
Content Type	Text
Resource Type	Article

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