Please wait, while we are loading the content...
Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shih-Hao Ou Yen-Cheng Lin Tay-Jyi Lin Chih-Wei Liu |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Electronics Engineering, National Chiao Tung University, Taiwan (Shih-Hao Ou; Yen-Cheng Lin; Tay-Jyi Lin; Chih-Wei Liu) |
| Abstract | Conventional timing-optimized synchronous circuit is designed and constrained by the longest critical path delay, i.e. the worst-case design. However, the path delay of the circuit is absolutely data-dependent. In the example of an 8-bit multiplier simulation, for the 10,000 random input patterns, only about 1% of the input patterns exercise the critical path. This fact motivates us to exploit data-dependent latency of the functional unit to achieve significant energy reduction with negligible performance degradation. In this paper, we propose a design flow for the energy-efficient, variable-latency functional unit which exploits the data-dependent latency. In the 8-bit signed Booth-Wallace multiplier simulation (clock period: 1.2ns @UMC 90nm CMOS cell library), the proposed design can save energy by 21% with only 0.17% performance degradation. Besides, compared to other popular energy reduction technique, the pipelined architecture, for the classical 5-stage RISC processor, the proposed technique improves about 23–28% energy-delay metric performance efficiency. |
| Starting Page | 4165 |
| Ending Page | 4168 |
| File Size | 319819 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424453085 |
| DOI | 10.1109/ISCAS.2010.5537593 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-05-30 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Energy efficiency Delay Clocks Energy consumption Timing Degradation Circuit synthesis Reduced instruction set computing Industrial electronics Data engineering |
| Content Type | Text |
| Resource Type | Article |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|