NDLI: Optical network-on-chip reconfigurable model for multi-level analysis

Content Provider	IEEE Xplore Digital Library
Author	Allam, A. O'Connor, I. Scandurra, A.
Copyright Year	2010
Description	Author affiliation: On Chip Communication Systems group, STMicroelectronics, Catania, Italy (Scandurra, A.) \|\| University of Lyon, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, France (Allam, A.; O'Connor, I.)
Abstract	Optical network-on-chip (ONoC) is a well accepted emerging technology for use as a communication platform for systems-on-chip (SoC). Its heterogeneous nature dictates developing a hierarchical model and tools for its design and analysis. This paper presents a reconfigurable ONoC model that can be used for analyzing the network at three hierarchical levels: system level, behavioral level, and physical level. At system level, the proposed ONoC model can be used to evaluate the network performance metrics (e.g. latency and throughput). At behavioral level, the model can be used to analyze the functionality of the whole ONoC from the interaction and the integration of its constituent building blocks. At the physical level, the model can be used to analyze the effect and verify the joint feasibility of optoelectronic and photonic devices specifications for reliable data communication and can further be used as a reference golden model during the design phase of the physical devices. The proposed model has been integrated successfully inside an industrial simulation environment (ST GenKit) using an industrial standard (VSTNoC) protocol.
Starting Page	3609
Ending Page	3612
File Size	291605
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537793
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optical fiber networks Network-on-a-chip Optical crosstalk Passive optical networks Microcavities Optical interconnections Delay Protocols Optical noise System-on-a-chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in