NDLI: Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops

Content Provider	IEEE Xplore Digital Library
Author	Mostafa, H. Anis, M. Elmasry, M.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L3G1 (Mostafa, H.; Anis, M.; Elmasry, M.)
Abstract	In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for delay, energy, and energy-delay product (EDP) overheads to achieve this power yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has the lowest overheads while the modified clocked CMOS master slave flip-flop $(M-C^{2}MOS-MSFF)$ exhibits the largest overheads, and correspondingly, it is not recommended for sub-threshold operation.
Starting Page	1739
Ending Page	1742
File Size	1850615
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537544
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Power dissipation CMOS technology Clocks Master-slave Threshold voltage Design methodology Random processes Circuit simulation Latches
Content Type	Text
Resource Type	Article

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