NDLI: A novel high-speed and low-power negative voltage level shifter for low voltage applications

Content Provider	IEEE Xplore Digital Library
Author	Peijun Liu Xueqiang Wang Dong Wu Zhigang Zhang Liyang Pan
Copyright Year	2010
Description	Author affiliation: Institute of Microelectronics, Tsinghua University, Beijing, China (Peijun Liu; Xueqiang Wang; Dong Wu; Zhigang Zhang; Liyang Pan)
Abstract	A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130nm 1.5V/5V triple-well CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of −4.5V. Simulation results show that the switching delay and power consumption have been significantly reduced by roughly 62% and 65%, respectively. In addition, the proposed level shifter realizes a wide operation margin with a lower VDD compared to conventional implementations.
Starting Page	601
Ending Page	604
File Size	500235
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537521
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low voltage Switches Delay Driver circuits Energy consumption MOS devices CMOS technology Negative feedback Charge pumps MOSFETs
Content Type	Text
Resource Type	Article

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