NDLI: 8×8-Bit multiplier designed with a new wave-pipelining scheme

Content Provider	IEEE Xplore Digital Library
Author	Sever, R. Askar, M.
Copyright Year	2010
Description	Author affiliation: Electrical & Electronics Engineering Department Middle East Technical University Ankara, Turkey (Askar, M.) \|\| Electrical & Electronics Engineering Department Akdeniz University Antalya, Turkey (Sever, R.)
Abstract	In this paper, a new wave-pipelining scheme is proposed. In classical wave-pipelining scheme, the data waves propagate on the circuit and the propagating waves are sampled simultaneously when they reach to a synchronization stage. In this new wave-pipelining scheme, only the components of the wave whose delay-difference values reach to a critical value are sampled. Other components, which are not sampled, are aligned with the sampled ones by using active delay elements. This wave-pipelining scheme significantly decreases the number of flip-flops which are used to synchronize the propagating waves. For demonstrating the effectiveness of the new wave-pipelining scheme, an 8×8-bit carry save multiplier is implemented using 0.35um standard CMOS process. Simulation results show that, the multiplier can operate at a speed of 2GHz, by using only 55 flip-flops. Comparing with the mesochronous pipelining scheme, the number of the flip-flops is decreased by 47%.
Starting Page	2095
Ending Page	2098
File Size	409502
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537223
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Logic Clocks Circuits Frequency synchronization Flip-flops Propagation delay Registers Design engineering CMOS process
Content Type	Text
Resource Type	Article

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