NDLI: Recursive architectures for 2DLNS multiplication

Content Provider	IEEE Xplore Digital Library
Author	Azarmehr, M. Ahmadi, M. Jullien, G.A.
Copyright Year	2010
Description	Author affiliation: University of Windsor, Research Center for Integrated Microsystems, Department of Electrical and Computer Engineering, 401 Sunset Avenue, Windsor, Ontario, N9B 3P4 (Azarmehr, M.; Ahmadi, M.; Jullien, G.A.)
Abstract	In the area of signal processing, digital circuits are advantageous in terms of lower sensitivity to noise and process variations, simplicity of design, programmability and test, while they attain higher speed, more functionality per chip, lower power dissipation or lower cost. Since some of DSP algorithms heavily rely on multiplication, there are constant demands for more efficient multiplication structures. In this paper, 2DLNS-based multiplication architectures with two different levels of recursion are presented. Our architectures combine some of the flexibility of software with the high performance of hardware through implementing the recursive multiplication schemes on a 2DLNS processing structure. The implementations demonstrate the efficiency of 2DLNS in DSP applications and show outstanding results in terms of operation delay and dynamic power consumption.
Starting Page	3869
Ending Page	3872
File Size	278105
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537705
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing algorithms Digital signal processing chips Circuit testing Computer architecture Digital circuits Circuit noise Signal design Power dissipation Cost function Software performance
Content Type	Text
Resource Type	Article

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