NDLI: To GPU synchronize or not GPU synchronize?

Content Provider	IEEE Xplore Digital Library
Author	Wu-chun Feng Shucai Xiao
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, Virginia Tech (Shucai Xiao) \|\| Department of Computer Science (Wu-chun Feng)
Abstract	The graphics processing unit (GPU) has evolved from being a fixed-function processor with programmable stages into a programmable processor with many fixed-function components that deliver massive parallelism. By modifying the GPU's stream processor to support “general-purpose computation” on the GPU (GPGPU), applications that perform massive vector operations can realize many orders-of-magnitude improvement in performance over a traditional processor, i.e., CPU. However, the breadth of general-purpose computation that can be efficiently supported on a GPU has largely been limited to highly dataparallel or task-parallel applications due to the lack of explicit support for communication between streaming multiprocessors (SMs) on the GPU. Such communication can occur via the global memory of a GPU, but it then requires a barrier synchronization across the SMs of the GPU in order to complete the communication between SMs. Although our previous work demonstrated that implementing barrier synchronization on the GPU itself can significantly improve performance and deliver correct results in critical bioinformatics applications, guaranteeing the correctness of inter-SM communication is only possible if a memory consistency model is assumed. To address this problem, NVIDIA recently introduced the threadfence() function in CUDA 2.2, a function that can guarantee the correctness of GPU-based inter-SM communication. However, this function currently introduces so much overhead that when using it in (direct) GPU synchronization, GPU synchronization actually performs worse than indirect synchronization via the CPU, thus raising the question of whether “to GPU synchronize or not GPU synchronize?”
Starting Page	3801
Ending Page	3804
File Size	977600
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537722
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Central Processing Unit Graphical processing unit Bioinformatics Parallel processing Computer science Application software Rendering (computer graphics) Interpolation Computer architecture Graphics processing unit
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

GPU as a General Purpose Computing Resource

Scalable Multi-GPU Decoupled Parallel Rendering Approach in Shared Memory Architecture

Parallel AES algorithm for fast Data Encryption on GPU

Functionality distribution for parallel rendering

Using GPU to exploit parallelism on cryptography

Enhancing Blowfish file encryption algorithm through parallel computing on GPU

Introduction to GPU programming for EDA

Multi-GPU Compositeless Parallel Rendering Algorithm

GPU based implementation of recursive digital filtering algorithms

To GPU synchronize or not GPU synchronize?

Similar Documents

GPU as a General Purpose Computing Resource

Scalable Multi-GPU Decoupled Parallel Rendering Approach in Shared Memory Architecture

Parallel AES algorithm for fast Data Encryption on GPU

Functionality distribution for parallel rendering

Using GPU to exploit parallelism on cryptography

Enhancing Blowfish file encryption algorithm through parallel computing on GPU

Introduction to GPU programming for EDA

Multi-GPU Compositeless Parallel Rendering Algorithm

GPU based implementation of recursive digital filtering algorithms

To GPU synchronize or not GPU synchronize?