NDLI: A scalable offset-cancelled current/voltage sense amplifier

Content Provider	IEEE Xplore Digital Library
Author	Attarzadeh, H. SharifKhani, M. Jahinuzzaman, S.M.
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering, Sharif University of technology, Tehran, Iran (Attarzadeh, H.; SharifKhani, M.) \|\| Department of Electrical and Computer Engineering, Concordia University, Montreal, Canada (Jahinuzzaman, S.M.)
Abstract	The application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. The offset cancellation phase takes place in parallel to the wordline decoding time in order to speed up the current sensing. The proposed scheme requires a small power budget due to a self shut off mechanism. In addition to presenting a comparison with the conventional schemes, the efficiency of the proposed scheme is evaluated in 90nm, 130nm and 180nm CMOS technologies to show the scalability and the robustness of the proposed scheme under smaller voltage headroom.
Starting Page	3853
Ending Page	3856
File Size	275570
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537701
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Energy consumption Random access memory Capacitance Robustness Resource description framework Circuits Threshold voltage Decoding Scalability
Content Type	Text
Resource Type	Article

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