NDLI: Phase amplitude converter with conditional shift operation

Content Provider	IEEE Xplore Digital Library
Author	Hikawa, H. Namba, T.
Copyright Year	2010
Description	Author affiliation: Kansai University, Dept. of Science and Engineering, 3-3-35 Yamate-cho, Suita-shi, Osaka 564-8680, Japan (Hikawa, H.; Namba, T.)
Abstract	This paper proposes a new type of approximation method for sine wave and the proposed method is applied to phase amplitude converter (PAC) used in direct digital frequency synthesizer (DDFS). The approximation is carried out by conditional shift operation (CSO) that reshapes the sawtooth signal from phase accumulator. As the signal purity of the CSO-PAC is not good enough, error correction is employed to improve the signal purity. VHDL simulations along with the circuit size and speed evaluations, are conducted to verify the feasibility of the proposed method. The comparison among other types of PACs shows that the advantage of the proposed PAC is its circuit size. Especially the CSO-PAC without the error correction, is quite small and it can operate at a very high frequency clock. Thus the CSO-PAC may be a good choice for those applications that do not require high purity signal.
Starting Page	3008
Ending Page	3011
File Size	372505
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5538000
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read only memory Frequency synthesizers Circuits Digital-to-frequency converters Error correction Adders Clocks Approximation methods Picture archiving and communication systems Table lookup
Content Type	Text
Resource Type	Article

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