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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Choudhary, N. Gaur, M.S. Laxmi, V. Singh, V. |
| Copyright Year | 2010 |
| Description | Author affiliation: Dept. of Computer Engineering, Malaviya National Institute of Technology, Jaipur, India (Choudhary, N.; Gaur, M.S.; Laxmi, V.) || Super Computer Education & Research Centre, Indian Institute of Science, Bangalore, India (Singh, V.) |
| Abstract | Network-on-Chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. The aim is to generate a custom NoC that maximizes performance under the given resource constraints. The paper presents a heuristic technique based on genetic algorithm for synthesis of custom NoC architectures along with requisite routing tables with the objective to improve communication load distributions in the network subject to the resource constraints in such a way that the overall communication throughput and latency improves. |
| Starting Page | 3156 |
| Ending Page | 3159 |
| File Size | 715784 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424453085 |
| DOI | 10.1109/ISCAS.2010.5537952 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-05-30 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Genetic algorithms Network topology Network-on-a-chip Routing System recovery Bandwidth Computer networks Character generation Application software Genetic engineering |
| Content Type | Text |
| Resource Type | Article |
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