NDLI: A multiple code-rate turbo decoder based on reciprocal dual trellis architecture

Content Provider	IEEE Xplore Digital Library
Author	Chen-Yang Lin Cheng-Chi Wong Hsie-Chia Chang
Copyright Year	2010
Description	Author affiliation: Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, R.O.C. (Chen-Yang Lin; Cheng-Chi Wong; Hsie-Chia Chang)
Abstract	To increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5.
Starting Page	1496
Ending Page	1499
File Size	948726
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537361
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Hardware Turbo codes Convolutional codes Throughput Computational modeling CMOS logic circuits Costs Multiaccess communication CMOS process
Content Type	Text
Resource Type	Article

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