NDLI: A VLSI design of sensor node for wireless image sensor network

Content Provider	IEEE Xplore Digital Library
Author	Renyan Zhou Leibo Liu Shouyi Yin Ao Luo Xinkai Chen Shaojun Wei
Copyright Year	2010
Description	Author affiliation: Research Center for Mobile Computing, Tsinghua University, Institute of Microelectronics, Tsinghua University Tsinghua National Laboratory for Information Science and Technology, Beijing 100084, China (Renyan Zhou; Leibo Liu; Shouyi Yin; Ao Luo; Xinkai Chen; Shaojun Wei)
Abstract	This paper presents a single chip VLSI architecture of wireless image sensor node, which is constituted by an enhanced embedded 8051 microcontroller, a CMOS camera interface and hardware accelerators. The algorithms and control flows of the IEEE 802.15.4 MAC layer are accelerated by hardware, results in 45% less code size compared with the conventional software stack. An innovated CFA preprocessing algorithm and JPEG-LS compressing method is adopted and implemented by hardware, which has a minimal 46.3dB PSNR, an average compression ratio of about 3.0bit/pixel and an approximately 5fps at 16MHz system clock. Furthermore, low power design and techniques are employed to extend battery life, resulting in 60mW max system power consumption when the SoC is in full working mode (i.e. processor, image processing and wireless communication are active simultaneously) in 0.18µm CMOS process.
Starting Page	149
Ending Page	152
File Size	305583
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5538037
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image sensors Wireless sensor networks Very large scale integration Hardware CMOS image sensors Image coding Computer architecture Microcontrollers Cameras Software algorithms
Content Type	Text
Resource Type	Article

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