NDLI: Application-level pipelining on Hierarchical NoC

Content Provider	IEEE Xplore Digital Library
Author	Yi Wei Pan Hongbing Pan Peng Li Li Gao Minglun Hou Ning Du Gaoming Zhang Duoli
Copyright Year	2010
Description	Author affiliation: VLSI Research Institute, Hefei University of Technology, Hefei, China (Hou Ning; Du Gaoming; Zhang Duoli) \|\| Inst. of VLSI Design, Nanjing University, Nanjing, China (Yi Wei; Pan Hongbing; Pan Peng; Li Li; Gao Minglun)
Abstract	Multiprocessor System-on-Chip is a promising solution for the high performance Embedded System. This paper is based on an independent research about Hierarchical NoC (Network-on-chip). By integrating 16 ARM cores in the FPGA board, we can bring out the four-channel fade-in and fade-out for real-time streaming media. We present two parallel models for our multiprocessor. One is fine-grained parallelization, with which the speed-up is 7.6, the other module is coarse-grained parallelization, with which the speed-up is higher than 9.2.
Starting Page	3873
Ending Page	3876
File Size	346454
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537706
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Network-on-a-chip Computer architecture Object oriented modeling SDRAM Very large scale integration Multicore processing System performance Hardware
Content Type	Text
Resource Type	Article

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