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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mohamed, A. Nadjia, A. |
| Copyright Year | 2013 |
| Description | Author affiliation: ESI (Ecole Nat. Super. d'Inf.), Algiers, Algeria (Mohamed, A.) || CDTA (Centre de Dev. des Technol. Av.), Baba Hassen, Algeria (Nadjia, A.) |
| Abstract | Enhancing Montgomery modular multiplication (MMM) performances in term of speed and area is crucial for public key cryptography applications. This paper presents an efficient hardware-algorithm for a high radix MMM method that exploits the features available in the Virtex-5 Xilinx FPGA. Our main contribution in this paper is to develop hardware algorithms for $radix-2^{16}$ number system in the FPGA to speed up the MMM. It performs an operation of two 1024-bits numbers on 64 iterations. The CS (Carry Save) representation is advantageously used to overcome the carry propagation then the iteration cycle datapath length independent. Specials efforts were made to design, at the LUT level, the compressor 6:2, which is the key feature of our design. The resulting architecture can run with clock period equivalent to the total delay of an embedded 18×18-bits and two LUT6. |
| Sponsorship | IEEE |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 242827 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781479935253 |
| DOI | 10.1109/IDT.2013.6727148 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-16 |
| Publisher Place | Morocco |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Montgomery modular multiplication FPGA Computer architecture Public key cryptography Hardware Delays Field programmable gate arrays Clocks |
| Content Type | Text |
| Resource Type | Article |
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