NDLI: IP-cores design for the kNN classifier

Content Provider	IEEE Xplore Digital Library
Author	Manolakos, E.S. Stamoulias, I.
Copyright Year	2010
Description	Author affiliation: Department of Informatics and Telecommunications, University of Athens Panepistimioupolis, Ilisia, 15784, Athens, Greece (Manolakos, E.S.; Stamoulias, I.)
Abstract	We present the systematic design of two linear array IP cores for the k-nearest neighbor (k-NN) benchmark classifier. The need for real-time classification of data vectors with possibly thousands of features (dimensions) motivates the implementation of this widely used algorithm in hardware in order to achieve very high performance by exploiting block pipelining and parallel processing. The two linear array architectures that we designed have been described as soft IP cores in fully parameterizable VHDL that can be used to synthesize effortlessly different k-NN parallel architectures for any desirable combination of the problem size parameters. They have been evaluated for a large variety of parameter combinations and Xilinx FPGAs. It is shown that they can be used to solve efficiently very large size k-NN classification problems, even with thousands of training vectors or vector dimensions, using a single, moderate size FPGA device. Furthermore the FPGA implementations exceed by a factor of two the performance of optimized NVIDIA CUDA API software implementations for the powerful GeForce 8800GTX GPU.
Starting Page	4133
Ending Page	4136
File Size	1104224
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Testing Hardware Vectors Pipeline processing Parallel architectures Nearest neighbor searches Parallel processing Error analysis Computer vision
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in