NDLI: Scaling analysis of yield optimization considering supply and threshold voltage variations

Content Provider	IEEE Xplore Digital Library
Author	Haghdad, K. Anis, M.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1, Canada (Haghdad, K.; Anis, M.)
Abstract	Parametric yield loss has become a significant issue in the design of nanometer integrated circuits (IC). In this paper, the impact of supply (Vdd) and threshold voltage (Vth) variations on the yield loss for the current and future CMOS technologies is investigated. The results demonstrate that, despite the temporary improvement due to the use of high-k dielectric materials and metal gates (HiK+MG), parametric yield and design robustness will remain amongst the major challenges in the future technology generations. Subsequently, design centers in the Vth-Vdd plane are suggested for having more robust and reliable circuits for the nodes. Monte-Carlo simulations using SPECTRE and HSPICE verify the provided results in this work for 90nm to 16nm nodes.
Starting Page	3665
Ending Page	3668
File Size	339304
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537773
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage CMOS technology Integrated circuit yield Integrated circuit technology Temperature Robustness Design optimization Space technology Uncertainty Fluctuations
Content Type	Text
Resource Type	Article

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