NDLI: Test application time minimization for RAS using basis optimization of column decoder

Content Provider	IEEE Xplore Digital Library
Author	Abhishek, A. Khan, A. Singh, V. Saluja, K.K. Singh, A.D.
Copyright Year	2010
Description	Author affiliation: University of Wisconsin-Madison, WI, USA (Saluja, K.K.) \|\| Indian Institute of Science, Bangalore, India (Abhishek, A.; Khan, A.; Singh, V.) \|\| Auburn University, Auburn, AL, USA (Singh, A.D.)
Abstract	Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random "care" bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2–3 times speed up in test write time compared to conventional RAS.
Starting Page	2614
Ending Page	2617
File Size	626578
Page Count	4
File Format	PDF
ISBN	9781424453085
DOI	10.1109/ISCAS.2010.5537094
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Circuit testing Flip-flops Vectors Performance evaluation Minimization Power dissipation Organizing Linear algebra Circuit simulation
Content Type	Text
Resource Type	Article

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