NDLI: Bridging technology-CAD and design-CAD for variability aware Nano-CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Harish, B.P. Bhat, N. Patil, M.B.
Copyright Year	2009
Description	Author affiliation: Dept. of Electrical Communication, Engg., Indian Institute of Science, Bangalore, India (Bhat, N.) \|\| Dept. of Electrical Engineering, UVCE, Bangalore University, India (Harish, B.P.) \|\| Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, India (Patil, M.B.)
Abstract	Transistor variability has emerged as one of the important constraints in Nano-CMOS circuit design. The ever decreasing device feature size with CMOS scaling, has resulted in an increasing uncertainty in predicting the exact device behaviour. The issue of variability needs to be addressed across the entire hierarchy of integrated circuits - optimization of process and device technology to yield minimal variability, robust circuit and system design architectures for variability aware design, and CAD tools to unify these two domains. The traditional variability modeling and CAD techniques address the problem in one of the two domains. We propose a unified framework to bridge the gap between technology CAD and design CAD. This framework enables one to directly relate the variation in circuit metrics such as speed, static power and dynamic power to the underlying semiconductor process parameters such as implant dose, annealing temperature etc. The proposed methodology is validated through rigorous simulations at the process, device and circuit level, incorporating various statistical techniques. A few examples will be presented to elaborate the significance of the proposed modeling methodology and its utility in the Nano CMOS design flow. In addition to being an important utility in the circuit design flow, the methodology will also help the foundries by providing a visibility on the impact of unit processes on the eventual circuit characteristics. This in turn can help in a systematic and optimized process monitoring in the foundries.
Starting Page	2309
Ending Page	2312
File Size	761253
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118261
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design automation CMOS technology Circuit synthesis Semiconductor process modeling Foundries Uncertainty Design optimization Integrated circuit technology Integrated circuit yield Robustness
Content Type	Text
Resource Type	Article

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