NDLI: Differential power analysis and differential fault attack resistant AES algorithm and its VLSI implementation

Content Provider	IEEE Xplore Digital Library
Author	Jia Zhao Jun Han Xiaoyang Zeng Liang Li Yunsong Deng
Copyright Year	2008
Description	Author affiliation: State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China (Jia Zhao; Jun Han; Xiaoyang Zeng; Liang Li; Yunsong Deng)
Abstract	This paper proposes an AES algorithm against both differential power analysis and differential fault analysis and its hardware implementation. This new algorithm emphasizes the feature of defending hardware against two kinds of side-channel attack simultaneously. Since the modified AES algorithm is much more complex than the original one, this paper exploits low hardware cost architecture to realize it. Furthermore, a pipelined structure is adopted to achieve high throughput. Simulations show that this architecture can protect hardware against both differential power analysis and differential fault attack. Synthesis result demonstrates that this design achieves adequately high data throughput with low hardware cost.
Starting Page	2220
Ending Page	2223
File Size	2436522
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4735012
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Very large scale integration Hardware Costs Doped fiber amplifiers Throughput Cryptography Information analysis Equations Application specific integrated circuits
Content Type	Text
Resource Type	Article

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