NDLI: High speed CMOS output stage for integrated DC-DC converters

Content Provider	IEEE Xplore Digital Library
Author	Wai Tung Ng Chang, M. Yoo, A. Langer, J. Hedquist, T. Schweiss, H.
Copyright Year	2008
Description	Author affiliation: Mater. Sci. & Eng., Univ. of Toronto, Toronto, ON, Canada (Yoo, A.) \|\| On Semicond. Inc., Phoenix, AZ, USA (Langer, J.; Hedquist, T.; Schweiss, H.) \|\| Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada (Wai Tung Ng; Chang, M.)
Abstract	A Hybrid Waffle layout technique is introduced for the design of CMOS power transistors in integrated low voltage DC-DC converters. Comparing with conventional multi-finger layout scheme, the Hybrid Waffle layout scheme allows optimized trade-off between device on-resistance and metal interconnect resistance to minimize overall on-resistance. Interestingly, the reduced channel width per unit area also leads to lower gate capacitance and faster switching speed. This paper presents a prototype DC-DC converter IC that contains integrated gate drivers, protection circuits and CMOS output transistors. Implemented in a standard 0.25 ¿m CMOS, this IC can be switched at 12.5 MHz with output current rated at 800 mA with input voltage of up to 4.2 V. Peak power efficiency of 85% was observed at 100 mA. Die size is 1.1 × 1.5 $mm^{2}.$
Starting Page	1909
Ending Page	1912
File Size	4492737
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4734950
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DC-DC power converters Power transistors Low voltage Prototypes Circuits Fingers Power conversion Switching converters Design engineering Power engineering and energy
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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