NDLI: Memory-efficient architecture including DWT and EC for JPEG2000

Content Provider	IEEE Xplore Digital Library
Author	Jie Guo Cheng-ke Wu Yun-song Li Ke-yan Wang Song, J.
Copyright Year	2008
Description	Author affiliation: State Key Lab. of Integrated Service Networks, Xidian Univ., Xi'an, China (Jie Guo; Cheng-ke Wu; Yun-song Li; Ke-yan Wang; Song, J.)
Abstract	In this paper, a memory-efficient and high-throughput VLSI architecture, which functionally includes discrete wavelet transform (DWT) and entropy coder (EC), is presented for JPEG2000 implementation. The proposed architecture is made up of line-based DWT using lifting scheme combined with the EC architecture performed in a bit plane parallel coding way. Based on this, an efficient memory strategy for wavelet transform coefficients connecting DWT and EC is designed, using on-chip memory units with the same size as a code block for an image tile with resolution 512×512 and code block size 32×32, the input sampling is up to 45 M pixels/s when EC operates at 100 MHz, yet the memory reduction is over 65%, compared with buffers for transform coefficients in tile size. Such features suit well applications for high-speed as well as low-memory, especially for large-tile image compression.
Starting Page	2192
Ending Page	2195
File Size	1147335
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4735005
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Memory architecture Discrete wavelet transforms Image coding Tiles Very large scale integration Entropy Joining processes Image resolution Image sampling Pixel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Memory-Saving System Including DWT and EC for JPEG2000 Implementation

An efficient VLSI architecture for JPEG2000 encoder

Efficient VLSI architecture of JPEG2000 encoder

Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder

Novel VLSI architecture of 2-D DWT/IDWT for JPEG2000 based on diagonal storage

Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000

An Efficient VLSI Implementation of Distributed Architecture for DWT

VLSI architecture of EBCOT tier-2 encoder for JPEG2000

An efficient VLSI implementation of DWT for JPEG2000

Memory-efficient architecture including DWT and EC for JPEG2000

Similar Documents

A Memory-Saving System Including DWT and EC for JPEG2000 Implementation

An efficient VLSI architecture for JPEG2000 encoder

Efficient VLSI architecture of JPEG2000 encoder

Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder

Novel VLSI architecture of 2-D DWT/IDWT for JPEG2000 based on diagonal storage

Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000

An Efficient VLSI Implementation of Distributed Architecture for DWT

VLSI architecture of EBCOT tier-2 encoder for JPEG2000

An efficient VLSI implementation of DWT for JPEG2000

Memory-efficient architecture including DWT and EC for JPEG2000