NDLI: Investigation of low cost consumer electronic system using 1066-Mb/s DDR2 interface design

Content Provider	IEEE Xplore Digital Library
Author	Nansen Chen Hongchin Lin
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan (Nansen Chen; Hongchin Lin)
Abstract	Low cost is always the favorite feature of consumer electronics. The purpose of this paper is to study the possibility of low-cost design for DDR2-1066 memory interface. The S-parameters simulations of the PCB, DDR2 controller and SDRAM packages were performed using the electromagnetic field solvers up to 3 GHz. Those broadband S-parameters were integrated with the chip SPICE models in the SPICE simulator for transient analyses. The results indicated that DDR2 command and control routing topology with zero series termination on the PCB and the controller using Level-7 drive strength encapsulated in the 2-layer PBGA package achieved 915-ps eye-aperture time, 507-ps signal skew, 2.14-V overshoot, and -0.37-V undershoot.
Starting Page	1203
Ending Page	1206
File Size	7573731
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4734763
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Consumer electronics Scattering parameters SPICE SDRAM Electronics packaging Electromagnetic fields Analytical models Transient analysis Command and control systems
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Integration Design of Chip and Package for Cost-Effective High-Speed Applications

Performance of low cost PBGA package for 10 Gb/s applications

A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface

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Investigation of low cost consumer electronic system using 1066-Mb/s DDR2 interface design

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