NDLI: The impact of stain technology on FUSI gate SOI CMOSFET and device performance enhancement for 45nm node and beyond

Content Provider	IEEE Xplore Digital Library
Author	Wen-Kuan Yeh Jean-An Wang Chien-Ting Lin Li-Wei Cheng Mike Ma
Copyright Year	2008
Description	Author affiliation: Central R&D Div., United Microelectron. Corp., Taiwan (Chien-Ting Lin; Li-Wei Cheng; Mike Ma) \|\| Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung, Taiwan (Wen-Kuan Yeh; Jean-An Wang)
Abstract	In this work, the impact of strain engineering on device performance and reliability for FUSI-gate SOI CMOSFET was investigated. With electrical measurement and reliability inspection, we found that there is similar enhancement on device performance, but different endurance on stressing induced device degradation for n/p MOSFET in respectively. Related noise analysis as well as charge pumping techniques were employed on the investigation of strain induced oxide defect which will accelerate device degradation after long time hot carrier stressing and/or bias instability stressing. And for manufacturability issue, a simple FUSI-metal-gate process with a fully compatible ultimate spacer process (USP) strain engineering is proposed for the first time. We found that channel mobility can be enhanced efficiently with about 28% and 40% $I_{ON}$ gain by the tensile-stress and compressive-stress CESL for n/pMOS, respectively.
Starting Page	130
Ending Page	133
File Size	6618746
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4734490
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology CMOSFETs Capacitive sensors Degradation Reliability engineering Electric variables measurement Stress measurement Inspection MOSFET circuits Charge pumps
Content Type	Text
Resource Type	Article

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Impact of oxide trap charge on performance of strained fully depleted SOI metal-gate MOSFET

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