NDLI: A 2-Bit 4GS/s flash A/D converter in 0.18 μm CMOS for an IR-UWB communication system

Content Provider	IEEE Xplore Digital Library
Author	Canxing Lu Lu Huang Wenjia Li
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China (Canxing Lu; Lu Huang; Wenjia Li)
Abstract	A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure is used without digital calibration which largely saves the power consumption, chip area and cost. And a differential resistive reference ladder is designed to minimize the inaccuracy of the reference voltage. The proposed ADC dissipates 34 mW power from a 1.8 V supply while operating at 4 GHz. This chip has been fabricated in 0.18 μm 1P6M CMOS process and the ADC achieves 1.86-bit effective number of bits (ENOB) for input signal of 1 GHz at 4 GS/s in simulation of FFT analysis.
Starting Page	1965
Ending Page	1968
File Size	1069069
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4734946
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Ultra wideband technology Receivers CMOS logic circuits Calibration Costs Voltage CMOS process Signal processing Analytical models CML UWB flash ADC low-swing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in