NDLI: The RF front-end single-chip SOI solution

Content Provider	IEEE Xplore Digital Library
Author	Pingxi Ma Racanelli, M.
Copyright Year	2008
Description	Author affiliation: Jazz Semicond., Newport Beach, CA, USA (Pingxi Ma; Racanelli, M.)
Abstract	In order to verify RF front-end single-chip solution, we have demonstrated several design cases for both Power Amplifier (PA) cells using SiGe HBTs and RF Switches (RFS) using CMOS technology on SOI. The PA-cell packaged has achieved 28 dBm linear output power with 36.2% PAE and more than 9.1dB gain at 836 MHz and 3.6 V. The PA-cell passes VSWR=10:1 ruggedness test at 4.2 V. With more on-wafer loadpulled results, we can qualify the PA-cell for CDMA/WCDMA applications. The RFS has on-wafer measured 0.5~1.5 dB insertion loss until 2.4 GHz and the packaged SP6T test [4] has reached >=34 dBc isolation and 1.4 dB insertion loss at 1.8 GHz with 41 dBm $P_{0.1dB}$ at 900 MHz. The design test has shown a promising perspective that the RF front-end single-chip solution will be capable of implementations based on Jazz¿s thick-film SOI SiGe BiCMOS technology platform.
Starting Page	1456
Ending Page	1459
File Size	5867990
Page Count	4
File Format	PDF
ISBN	9781424421855
DOI	10.1109/ICSICT.2008.4734840
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency Testing Power amplifiers Silicon germanium Germanium silicon alloys CMOS technology Packaging Multiaccess communication Insertion loss Radiofrequency amplifiers
Content Type	Text
Resource Type	Article

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