NDLI: FPGA implementation of hardware processing modules as coprocessors in brain-machine interfaces

Content Provider	IEEE Xplore Digital Library
Author	Dong Wang Yaoyao Hao Xiaoping Zhu Ting Zhao Yiwen Wang Yaowu Chen Weidong Chen Xiaoxiang Zheng
Copyright Year	2011
Description	Author affiliation: Qiushi Academy for Advanced Studies, Zhejiang University, Hangzhou, China (Ting Zhao; Yiwen Wang) \|\| Qiushi Academy for Advanced Studies, and College of Computer Science and Technology, Zhejiang University, Hangzhou, China (Weidong Chen) \|\| Qiushi Academy for Advanced Studies, the Department of Biomedical Engineering and Instrument Science, Zhejiang University, HangZhou, China (Xiaoxiang Zheng) \|\| Qiushi Academy for Advanced Studies, and the Department of Biomedical Engineering and Instrument Science, Zhejiang University, Hangzhou, China (Dong Wang; Yaoyao Hao) \|\| Institute of Advanced Digital Technologies & Instrumentation, Zhejiang University, Hangzhou, China (Xiaoping Zhu; Yaowu Chen)
Abstract	Real-time computation, portability and flexibility are crucial for practical brain-machine interface (BMI) applications. In this work, we proposed Hardware Processing Modules (HPMs) as a method for accelerating BMI computation. Two HPMs have been developed. One is the field-programmable gate array (FPGA) implementation of spike sorting based on probabilistic neural network (PNN), and the other is the FPGA implementation of neural ensemble decoding based on Kalman filter (KF). These two modules were configured under the same framework and tested with real data from motor cortex recording in rats performing a lever-pressing task for water rewards. Due to the parallelism feature of FPGA, the computation time was reduced by several dozen times, while the results are almost the same as those from Matlab implementations. Such HPMs provide a high performance coprocessor for neural signal computation.
Starting Page	4613
Ending Page	4616
File Size	564010
Page Count	4
File Format	PDF
ISBN	9781424441211
ISSN	1557170X
e-ISBN	9781457715891
e-ISBN	9781424441228
DOI	10.1109/IEMBS.2011.6091142
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Decoding Sorting Hardware Computer architecture Kalman filters Random access memory
Content Type	Text
Resource Type	Article
Subject	Signal Processing Biomedical Engineering Health Informatics Computer Vision and Pattern Recognition

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