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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Weiyang Qiu Kailin Pan Chaoping Yuan Jiaopin Wang |
| Copyright Year | 2009 |
| Description | Author affiliation: School of Mechanical and Electrical Engineering, Guilin University of Electronic Technology No.1 Jinji Road, Guilin, China, 541004 (Weiyang Qiu; Kailin Pan; Chaoping Yuan; Jiaopin Wang) |
| Abstract | Embedded passives represent a promising solution regarding the reduction of size and assembly costs of system in package (SiP). In addition, the benefits also include improvements in electrical performance and reliability. Although embedded passives are more reliable by elimination solder joint interconnects, they also introduce other concerns such as deformation and component instability. More layers may be needed to accommodate the embedded passives, and various materials within the substrate may cause significant thermo-mechanical stress due to coefficient of thermal expansion (CTE) mismatch. Due to the embedded substrate include viscoelastic material, the Maxwell model was applied to describe the viscoelastic behavior of embedded capacitor in the FR4 substrate series, and the constitutive equations of the Maxwell model were obtained. The three dimensional finite element model of embedded capacitor is developed. And the thermo-mechanical deformation of embedded capacitor is investigated after accelerated thermal cycling (−55°C to 125°C) based on the American military standard (MIL). The result shows that the maximum displacement takes place at the both sides of the middle edges. And the deformation leads to the distance of capacitor electrodes increase, which results in decrease of capacitance. The biggest reduction of capacitance is approximate 10% after thermal cycling, but embedded substrate is baked before thermal cycling can prevent the capacitance from decreasing and the change of capacitor is less than 5%. From 100MHz to 1GHz, the signal integrity of micro-via is investigated and the model is developed. The signal micro-via including one ground-via have obvious resonance peaks around the 1GHz. Compare with one ground-via, the resonant peak of micro-via including four ground-via that array symmetrically can be inhibited. In addition, the insertion loss and return loss of the micro-via including four ground-vias are less than that including only one ground-via. |
| Starting Page | 123 |
| Ending Page | 127 |
| File Size | 1296295 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424446582 |
| DOI | 10.1109/ICEPT.2009.5270779 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-08-10 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitors Capacitance Thermomechanical processes Thermal stresses Viscosity Elasticity Resonance Assembly systems Costs Packaging |
| Content Type | Text |
| Resource Type | Article |
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