NDLI: Parametric study of electroplating-based via-filling process for TSV applications

Content Provider	IEEE Xplore Digital Library
Author	Tsui, K.Y.K. Yau, S.K. Leung, V.C.K. Sun, P. Shi, D.X.Q.
Copyright Year	2009
Description	Author affiliation: Hong Kong Applied Science & Technology Research Institute (ASTRI) 2 Science Park East Avenue, Hong Kong Science Park, Shatin, New Territories, Hong Kong, China (Tsui, K.Y.K.; Yau, S.K.; Leung, V.C.K.; Sun, P.; Shi, D.X.Q.)
Abstract	In this study, the effects of different influence factors on electroplating-based via-filling process were studied in a systematic manner. A through-silicon-via (TSV) chip was firstly designed, the chip size was $16×10mm^{2}$ with the TSV interconnects. The via was in diameter of 50μm and depth of 75μm. The deep reactive ion etching (DRIE) technique was employed to fabricate the vias onto the silicon wafer. In order to fill up the vias by using the electroplating process, the SiO2 isolation layer was firstly prepared onto the sidewall and the defined surface of the wafer using the plasma enhanced chemical vapor deposition (PECVD) technique, the TiW barrier layer was prepared onto the SiO2 layer with the sputtering process, the Cu seed layer was then deposited onto the barrier layer by the sputtering process to provide a foundation for copper growth during electroplated deposition. To achieve the “bottom-up” via-filling, the addictives were added into the copper plating solution. The results showed that the void free Cu filling can be achieved with an optimal additives ratio. The variation in both via opening and depth were found to be key factors influencing the via-filling quality. The process parameters such as current density, power waveform and so on were found to affect the vial filling quality. A comparison on the effects of key process parameters was made, showing that the current density, voltage waveform, and pulse reserve are three key parameters that affect the filling quality more than other parameters.
Starting Page	23
Ending Page	27
File Size	1022277
Page Count	5
File Format	PDF
ISBN	9781424446582
DOI	10.1109/ICEPT.2009.5270801
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-10
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parametric study Through-silicon vias Copper Filling Sputtering Current density Etching Silicon Plasma applications Plasma chemistry
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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