NDLI: Full thermal parametric model for power WL-CSP design

Content Provider	IEEE Xplore Digital Library
Author	Zhongfa Yuan Yong Liu Martin, S. England, L. Byoungok Lee
Copyright Year	2009
Description	Author affiliation: Fairchild Semiconductor, Suzhou, China (Zhongfa Yuan) \|\| Fairchild Semiconductor Corp., S. Portland, USA (Yong Liu; Martin, S.; England, L.) \|\| Fairchild Semiconductor, Bucheon, Korea (Byoungok Lee)
Abstract	A new type of full thermal parametric model for power wafer level chip scale package (WL-CSP) is developed in this paper, which includes parametric WL-CSP and its adaptive parametric JEDEC thermal test board. By employment of the parametric model, package geometry parameters and the trace layout for PCB can easily be changed to meet the requirement of design, so that the influence of all geometry parameters to thermal performance can be investigated fast for the whole series of WL-CSP packages. The entire thermal simulation, including meshing, loading/boundary condition, solving, and post processing, is automated with ANSYS® parametric design language (APDL) coding. This paper introduces the construction of the parametric model for WL-CSP design, and both JEDEC low effective thermal board and high effective thermal conductivity boards with and without thermal vias are included in the model. To study impact of solder ball number, die size, terminal pitch on thermal resistances or parameters, extensive modeling tasks are run and related results are systemically investigated. As verification, a WL-CSP with 6 balls is actually tested finally, and results show that it is a good match between actual measurement and simulation results.
Starting Page	304
Ending Page	310
File Size	1535444
Page Count	7
File Format	PDF
ISBN	9781424446582
DOI	10.1109/ICEPT.2009.5270744
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-10
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parametric statistics Thermal conductivity Wafer scale integration Testing Geometry Chip scale packaging Employment Thermal loading Boundary conditions Thermal resistance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Wafer level chip scale packaging (WL-CSP): an overview

Parametric design study for minimized warpage of WL-CSP

Encapsulated double-bump WL-CSP: design and reliability

Encapsulant materials and processes for wafer level-chip scale packaging (WL-CSP)

Improvement in WL-CSP reliability by wafer thinning

Wafer-level chip size package (WL-CSP)

Dynamic substructure method for prediction of solder joint reliability of IC package under drop test

WLCSP parameter study for ball reliability analysis

Low cost wafer-level CSP: a novel redistribution methodology

Full thermal parametric model for power WL-CSP design

Similar Documents

Wafer level chip scale packaging (WL-CSP): an overview

Parametric design study for minimized warpage of WL-CSP

Encapsulated double-bump WL-CSP: design and reliability

Encapsulant materials and processes for wafer level-chip scale packaging (WL-CSP)

Improvement in WL-CSP reliability by wafer thinning

Wafer-level chip size package (WL-CSP)

Dynamic substructure method for prediction of solder joint reliability of IC package under drop test

WLCSP parameter study for ball reliability analysis

Low cost wafer-level CSP: a novel redistribution methodology

Full thermal parametric model for power WL-CSP design