NDLI: Encapsulated double-bump WL-CSP: design and reliability

Content Provider	IEEE Xplore Digital Library
Author	Keser, B. Yeung, B. White, J. Fang, T.
Copyright Year	2001
Description	Author affiliation: Motorola SPS, Tempe, AZ, USA (Keser, B.)
Abstract	A new type of wafer level package has been designed and fabricated by using an encapsulation material, which is applied directly to a bumped wafer, thereby eliminating the underfill process, and protecting all the bumps on the wafer at once in a batch process. This material was designed to have the necessary elastic modulus and coefficient of thermal expansion required by this application. After application of the encapsulation, the wafer is then bumped again with C5 balls, creating a double bump structure that increases the overall bump height to improve the reliability further. Redistribution of bondpads from the die periphery to an area array using BCB and redistribution metal aids in eliminating the need for an interposer. This wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8/spl times/8 array of bumps on a 5/spl times/5 mm/sup 2/ die. Micro Moire Interferometry has shown that the encapsulation layer facilitates the distribution of stress throughout the wafer level bumps. The bump structure and package geometry have been optimized using simulation and validated by experimentation to insure contact between the encapsulation and first level bump, which is key to reducing stress and improving reliability. Initial package and board level reliability data are reported.
Sponsorship	Components, Packaging, & Manuf. Technol. (CPMT) Soc. IEEE
Starting Page	35
Ending Page	39
File Size	1795995
Page Count	5
File Format	PDF
ISBN	0780370384
ISSN	05695503
DOI	10.1109/ECTC.2001.927679
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Encapsulation Stress Protection Thermal expansion Wafer bonding Chip scale packaging Testing Vehicles Interferometry
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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