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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Di Wu Yun Chen Qichen Zhang Lirong Zheng Xiaoyang Zeng Yeong-luh Ueng |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Yeong-luh Ueng) || State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China (Di Wu; Yun Chen; Qichen Zhang; Lirong Zheng; Xiaoyang Zeng) |
| Abstract | Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology. |
| Starting Page | 3044 |
| Ending Page | 3047 |
| File Size | 751541 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7169329 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Decoding Parity check codes Radiation detectors Bit error rate High definition video Throughput Hardware Stochastic decoding Bit-Flipping Algorithm Low-Density Parity-Check Codes High-throughput Decoder |
| Content Type | Text |
| Resource Type | Article |
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