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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ahmed, M. Shah, I. Fang Tang Bermak, A. |
| Copyright Year | 2015 |
| Description | Author affiliation: Coll. of Commun. Eng., Chongqing Univ. (CQU), Chongqing, China (Fang Tang) || Dept. of ECE, Hong Kong Univ. of Sci. & Technol., Hong Kong, China (Ahmed, M.; Shah, I.; Bermak, A.) |
| Abstract | An improved recycling folded cascode operational transconductance amplifier with gain boosting and enhanced phase-margin is proposed. Among four variants of folded cascode amplifiers that have been implemented in TSMC 0.18μm CMOS process under same power and area constraints, the proposed amplifier achieves the lowest settling error of less than 0.5% compared to 1.1% settling error by Improved Recycling Folded Cascode (IRFC), 1.4% settling error by Recycling Folded Cascode (RFC) and 30% settling error by conventional Folded Cascode (FC) amplifier. This performance enhancement is attributed to 30dB increment in low-frequency gain and 7° improvement in the phase margin when compared with the second best performing Improved Recycling Folded Cascode amplifier. |
| Starting Page | 2473 |
| Ending Page | 2476 |
| File Size | 510347 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7169186 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Recycling Transistors Transconductance CMOS process Noise Gain Mirrors phase margin enhancement Improved recycling folded cascode amplifier Gain boosting |
| Content Type | Text |
| Resource Type | Article |
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