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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bayat, F.M. Guo, X. Om'mani, H.A. Do, N. Likharev, K.K. Strukov, D.B. |
| Copyright Year | 2015 |
| Description | Author affiliation: Stony Brook Univ., Stony Brook, NY, USA (Likharev, K.K.) || A Subsidiary of Microchip Technol. Inc., Silicon Storage Technol. Inc., San Jose, CA, USA (Om'mani, H.A.; Do, N.) || UC Santa Barbara, Santa Barbara, CA, USA (Bayat, F.M.; Guo, X.; Strukov, D.B.) |
| Abstract | We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 $μm^{2}.$ While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in state-of-the-art analog circuit implementations. The new memory cell arrays have been successfully tested, in particular confirming that each cell may be automatically tuned, with ~1% precision, to any desired subthreshold readout current value within an almost three-orders-of-magnitude dynamic range, even using an unoptimized tuning algorithm. Preliminary results for a four-quadrant vector-by-matrix multiplier, implemented with the modified memory array, gate-coupled with additional peripheral floating-gate transistors, show highly linear transfer characteristics over a broad range of input currents. |
| Starting Page | 1921 |
| Ending Page | 1924 |
| File Size | 726939 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7169048 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Nonvolatile memory Logic gates Arrays Tuning Programming Transistors Flash memories Vector-matrix multiplier Floating-gate memory Analog memory Analog computing |
| Content Type | Text |
| Resource Type | Article |
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