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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kin-Chu Ho Chih-Lung Chen Yen-Chin Liao Hsie-Chia Chang Chen-Yi Lee |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Kin-Chu Ho; Chih-Lung Chen; Yen-Chin Liao; Hsie-Chia Chang; Chen-Yi Lee) |
| Abstract | As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces. |
| Starting Page | 1450 |
| Ending Page | 1453 |
| File Size | 2217249 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479983919 |
| DOI | 10.1109/ISCAS.2015.7168917 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-24 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Decoding Error correction codes Bit error rate Parity check codes Ash Hardware Throughput NAND Flash memory LDPC codes Solid State Drive |
| Content Type | Text |
| Resource Type | Article |
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