NDLI: Pre-processing power traces to defeat random clocking countermeasures

Content Provider	IEEE Xplore Digital Library
Author	Hodgers, P. Hanley, N. O'Neill, M.
Copyright Year	2015
Description	Author affiliation: Centre for Secure Inf. Technol. (CSIT), Queen's Univ. Belfast, Belfast, UK (Hodgers, P.; Hanley, N.; O'Neill, M.)
Abstract	We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.
Starting Page	85
Ending Page	88
File Size	929419
Page Count	4
File Format	PDF
ISBN	9781479983919
DOI	10.1109/ISCAS.2015.7168576
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-24
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Power demand Cryptography Computer science Correlation Smart cards Hardware FPGA power analysis attacks random clocking
Content Type	Text
Resource Type	Article

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