NDLI: Architecture of the modified Block-Type Low-Density parity-check code decoding design

Content Provider	IEEE Xplore Digital Library
Author	Kuang-Hao Lin Chang, R.C. Sheng-Dong Wu
Copyright Year	2007
Description	Author affiliation: Nat. Chung Hsing Univ., Taichung (Kuang-Hao Lin; Chang, R.C.; Sheng-Dong Wu)
Abstract	In this paper, a combined Low-Density Parity- Check (LDPC) code decoding design method, called modified Block-Type LDPC (B-LDPC), for realistic LDPC coding system architectures is presented. The B-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified B-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and achievable architecture implementation. The modified B-LDPC code decoding utilizes the iterative min-sum algorithm (MSA) and its decoding architecture design employs the non-overlapping operations of bit node unit (BNU) and check node unit (CNU). Different block matrix sizes for parity-check matrix can be adopted so that the modified B-LDPC code decoding improves the throughput without obvious performance degradation.
Starting Page	1
Ending Page	4
File Size	425836
Page Count	4
File Format	PDF
ISBN	9781424409822
DOI	10.1109/ICICS.2007.4449728
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Iterative decoding Hardware Digital communication Error correction AWGN Iterative algorithms Throughput Error analysis Bit error rate hardware architecture Low-Density Parity-Check (LDPC) decoder encoder
Content Type	Text
Resource Type	Article

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